The present invention relates generally to a semiconductor device and more particularly to a semiconductor device having circuitry using insulated gate field effect transistors (IGFETs) and improving leakage current through such devices.
As sizes on devices such as metal oxide semiconductor field effect transistors (MOSFETs) have become smaller, device isolation techniques, such as conventional LOCOS (local oxidation of silicon), have been replaced with a STI (shallow trench isolation) method.
In FIG. 8(a), a top plan view of the layout of a conventional MOSFET is set forth. In FIG. 8(b), a cross-sectional view along the line Axe2x80x94A of conventional MOSFET is set forth.
Referring now to FIG. 8(a), the conventional MOSFET includes an active area ACT. The active area ACT defines the region in which the conventional MOSFET is to be confined. A polysilicon wiring POL crosses the active area to form a gate electrode GG. Impurities are implanted and diffused into the active area ACT on both sides of the polysilicon wiring POL to form a drain region DD and source region SS. STI is formed in an area surrounding the active area ACT in order to isolate the conventional MOSFET from other device elements. The STI is not illustrated in FIG. 8(a).
Referring now to FIG. 8(b), a cross sectional view along the line Axe2x80x94A of the conventional MOSFET of FIG. 8(a) is set forth.
As illustrated in FIG. 8(b), a gate oxide film GOX is formed as a gate isolation film on the semiconductor substrate SUB over the active area ACT. Polysilicon wiring POL forming the gate electrode GG is formed on top of the gate oxide film GOX across the active area ACT. Although not illustrated in FIG. 8(b), the drain and source regions are formed on both sides of the gate GG in the active area ACT. A trench is formed around the active area ACT and silicon oxide SOX is formed within the trench to form the STI structure.
As device structures continue to become smaller due to miniaturization, the gate width as well as the thickness of the gate oxide film GOX and gate length are reduced. In the case of a conventional MOSFET, which uses LOCOS as the isolation structure, the threshold voltage tends to rise due to a narrow channel effect when a gate width is reduced. On the other hand, in the case of a conventional MOSFET, which uses STI as the isolation structure, the threshold voltage tends to decrease near the boundary between the active area ACT and the STI (field area). This threshold voltage fluctuation will be described with reference to FIG. 9.
Referring now to FIG. 9, a cross-sectional view of a region of the conventional MOSFET illustrated in FIG. 8 is set forth. The region illustrated in FIG. 9, is the portion indicated by general reference character K in FIG. 8 and is a portion including a boundary between the active area ACT and the STI. The cross-sectional view of FIG. 9, illustrates a n-type MOSFET.
As illustrated in FIG. 9, the STI is the vertically formed silicon oxide SOX. In the case of a n-type MOSFET a p-type impurity such as boron (illustrated by B) is included in the substrate. At the interface region between the active area ACT and the silicon oxide SOX, boron B can out-diffuse and become trapped in the silicon oxide SOX. As a result, the impurity density is reduced around the boundary between the active area ACT and the STI. This causes the threshold voltage of the MOSFET to decrease in this area and can create an increase leakage current in this region.
Also, a ridge T in silicon oxide can be formed at the interface between the gate oxide GOX and silicon oxide SOX formed in the STI. The ridge T can cause an increased electric field produced in the region around the boundary of active area ACT and STI.
Thus, in the threshold voltage tends to be lower in the region near the boundary of the active region ACT and the STI structure. Also, the electric field in this region may be increased due to a ridge T produced in the silicon oxide. These effects can cause an increase in sub-threshold currents in this area, which increases power consumption.
On the other hand, when a LOCOS structure is used for device isolation, the field oxide region next to the active area ACT may be an arc or bird beak type structure. Thus, with the lower surface area at the interface, a smaller amount of impurities may out-diffuse from the channel area to the field area and the leakage current may not be increased to the same degree.
However, as disclosed in Japanese Patent Application Laid-Open 9-321277, it is pointed out that the threshold voltage tends to decrease when the LOCOS structure is used as well as when the STI structure is used.
Thus, in a conventional MOSFET, it is known that leakage current can be increased around the boundary between the active area ACT and a field area (such as STI or LOCOS). This is particularly the case when the gate width is reduced. To suppress the leakage current, methods have been disclosed in Japanese Patent Application Laid-Open No. 9-321277 and Japanese Patent Application Laid Open no. 2000-82808. The approach disclosed in Japanese Patent Application Laid-Open No. 9-321277 uses a leveled profile in the depth direction of a threshold voltage control layer. The approach disclosed in Japanese Patent Application Laid-Open No. 2000-82808 uses a barrier layer to suppress the out-diffusion of impurities.
However, in the above-mentioned conventional approaches, the method of suppressing the leakage current due to the decrease in gate width is accomplished by modifying the device structure. The modification of the device structure may be difficult from a process view-point and may not be effective due to non-ideal process results. This is particularly the case when used in a circuit that is manufactured in large quantities. Thus it can be difficult to effectively suppress the leakage current with these approaches. Also, when these methods are used, the average threshold voltage in a device may increase. This can lower the current driving ability of the MOSFET. In this way, the circuit operating speed is reduced.
Referring now to FIG. 10, a circuit schematic diagram of a conventional predecoder is set forth. The conventional predecoder is used to select a word line formed in a memory cell array in a semiconductor memory device. The conventional predecoder illustrated in FIG. 10, can be illustrative of a circuit in which sub-threshold leakage can cause undesired current consumption. The sub-threshold current leakage can be greatly magnified by the fact that such a conventional predecoder may be repeated a large number of times on a typical semiconductor memory device.
The conventional predecoder of FIG. 10 includes NAND gate circuits (GJ1 to GJ4). NAND gate circuits (GJ1 to GJ4) commonly receive address signal A and respectively receive activating address signals (B1 to B4). Address signal A is used to collectively select NAND gate circuits (GJ1 to GJ4) and address signals (B1 to B4) are used to individually select one of NAND gate circuits (GJ1 to GJ4). NAND gate circuits (GJ1 to GJ4) respectively produce output signals (D1 to D4).
Each NAND gate circuit (GJ1 to GJ4) has p-type MOSFETs (PJ1 and PJ2) and n-type MOSFETs (NJ1 and NJ2). P-type MOSFET PJ1 has a source connected to a power supply, a drain connected to the respective output node (D1 to D4) and a gate connected to address signal A. P-type MOSFET PJ2 has a source connected to a power supply, a drain connected to the respective output node (D1 to D4) and a gate connected to the respective address signal (B1 to B4). N-type MOSFET NJ1 has a source connected to a drain of n-type MOSFET NJ2, a drain connected to the respective output node (D1 to D4) and a gate connected to address signal A. N-type MOSFET NJ2 has a source connected to ground and a gate connected to the respective address signal (B1 to B4).
In the conventional predecoder, only one of NAND gate circuits (GJ1 to GJ4) is selected at one time. Thus, when address signal A is high, only one of address signals (B1 to B4) is high and only one NAND gate circuit (GJ1 to GJ4) produces a low output signal (D1 to D4).
A plurality of such conventional predecoders is provided on a semiconductor memory device and any one of the NAND gate circuits (GJ1 to GJ4) in each conventional predecoder is selected in accordance with the value of address signal A and address signals (B1 to B4).
In the standby mode, address signal A is fixed at a low level. Thus, all NAND gate circuits (GJ1 to GJ4) are placed in a non-selection state and all output signals (D1 to D4) are fixed at a high level by the respective MOSFET PJ1. At this time, the address signals (B1 to B4) are fixed at either a low or high level depending on the configuration of the circuit generating these signals. In this example, to illustrate a worst case leakage current, all address signals (B1 to B4) are fixed at the high level.
Thus, in the standby mode with address signal A at a low level and address signals (B1 to B4) at a high level, in each NAND gate circuit (GJ1 to GJ4) the n-type MOSFET NJ1 is turned off and the n-type MOSFET NJ2 is turned on. As a result, a power source potential is applied to the drain and a ground potential is applied to the source of n-type MOSFET NJ1. Under these conditions, the leakage current in the area around the boundary between the active area and field area (isolation area) of n-type MOSFET NJ1 can become problematic. This leakage current can occur in all such circuits that are biased in this manner during standby. Also, the leakage current created by this mechanism can increase proportionally to the circuit scale.
In view of the above discussion, it would be desirable to provide a semiconductor device that can effectively reduce the leakage current that may be caused by the reduction of the gate width of an insulated gate field effect transistor (IGFET). It would also be desirable to effectively decrease the leakage current without having adverse affects on the device operating speed.
According to the present embodiments, a semiconductor device includes a plurality of logic circuits and an insulated gate field effect transistor (IGFET). The IGFET may have a current path connected between each of the logic circuits and a reference supply node. Each logic circuit may have a logic output node that may be at a potential different than the reference supply when the IGFET is turned off. The IGFET may have a counter measure to reduce leakage caused by short channel effects when the IGFET is turned off. In this way, leakage current may be reduced.
According to one aspect of the embodiments, a semiconductor device may include a first IGFET having a first IGFET current path connected between a first node and a second node fixed at a first predetermined potential. The first IGFET may include a counter measure to reduce leakage current caused by short channel effects when the first IGFET is turned off. The first node may be at a second predetermined potential.
According to another aspect of the embodiments, a second IGFET may have a second IGFET current path connected between the first node and the first IGFET current path. The first IGFET may have a larger resistance to leakage current than the second IGFET.
According to another aspect of the embodiments, the countermeasure may be providing fewer first regions in which a first gate electrode overlaps a boundary between a first IGFET active region and a field region in the first IGFET than second regions in which a second gate electrode overlaps a boundary between a second IGFET active region and the field region in the second IGFET.
According to another aspect of the embodiments, the second IGFET may include a plurality of IGFETs connected in parallel to function as the second IGFET.
According to another aspect of the embodiments, the countermeasure may include providing a first IGFET gate electrode having a longer first IGFET gate length in a region in which the first gate electrode overlaps a boundary between a first IGFET active region and a field region than in a central region of the first IGFET.
According to another aspect of the embodiments, the countermeasure may include providing a first IGFET gate electrode having a ring shaped pattern.
According to another aspect of the embodiments, the counter measure may include having a higher impurity concentration in a region in which the first gate electrode overlaps a boundary between a first IGFET active region and a field region than in a central region of the first IGFET.
According to another aspect of the embodiments, a semiconductor device may include a plurality of logic circuits. A first reference supply node may provide a first predetermined potential to the plurality of logic circuits. A first IGFET may have a first IGFET current path connected between each of the logic circuits and the first reference supply node. Each logic circuit may include a logic output node that may be at a second potential different than the first predetermined potential when the first IGFET is turned off.
According to another aspect of the embodiments, each logic circuit may be a NND gate including a plurality of p-type IGFETs connected in parallel between a second reference supply node and the logic output node and at least one n-type IGFET connected between the logic output node and the first IGFET. The first IGFET may be a n-type IGFET and the semiconductor device may be a semiconductor memory device.
According to another aspect of the embodiments, the first IGFET may include a counter measure to reduce leakage current caused by short channel effects when the first IGFET is turned off.
According to another aspect of the embodiments, the counter measure may include providing fewer first regions in which a first gate electrode overlaps a boundary between a first IGFET active region and a field region in the first IGFET than second regions in which a second gate electrode overlaps a boundary between a second IGFET active region and the field region in a second IGFET connected between the first IGFET and the logic output node in at least one of the plurality of logic circuits.
According to another aspect of the embodiments, the counter measure may include providing a first IGFET gate electrode having a longer first IGFET gate length in a region in which the first gate electrode overlaps a boundary between a first IGFET active region and a field region than in a central region of the first IGFET.
According to another aspect of the embodiments, the counter measure may include providing a first IGFET gate electrode having a ring shaped pattern.
According to another aspect of the embodiments, the counter measure may include a first threshold voltage of the first IGFET that is higher than a second threshold voltage of a second IGFET connected between the first IGFET and the logic output node in at least one of the plurality of logic circuits.
According to another aspect of the embodiments, a semiconductor device may include a plurality of logic circuits electrically connected in series and divided into a first group of logic circuits and second group of logic circuits. A first reference supply node may provide a first predetermined potential to the plurality of logic circuits. A second reference supply node may provide a second predetermined potential to the plurality of logic circuits. A first conductivity type IGFET may have a current path connected between each of the first group of logic circuits and the second reference supply node. The first group of logic circuits may be connected to the second reference supply node and the second group of logic circuits may be connected to the first reference supply node.
According to another aspect of the embodiments, the first conductivity type IGFET may include a counter measure to reduce leakage current when turned off.
According to another aspect of the embodiments, the counter measure may include providing fewer first regions in which a first gate electrode overlaps a boundary between a first active region and a field region in the first conductivity type IGFET than second regions in which a second gate electrode overlaps a boundary between a second active region and the filed region in another first conductivity type IGFET connected between the first conductivity type IGFET and a logic output node in at least one of the first group of logic circuits.
According to another aspect of the embodiments, the counter measure may include providing a first gate electrode having a longer gate length in a region in which the first gate electrode overlaps a boundary between a first active region and a field region than in a central region of the first conductivity type IGFET.
According to another aspect of the embodiments, the counter measure may include providing a first gate electrode having a ring shaped pattern.
According to another aspect of the embodiments, the first conductivity type may be n-type. The second conductivity type may be p-type. All IGFETs may be metal oxide semiconductor field effect transistors (MOSFETs).